VMIVME-4512 Glitches on DAC Outputs


The VMIVME-4512 Digital to Analog Conversion (DAC) update timing can be affected by accesses from the VME bus. The DAC timing state machine on the 4512 is driven by a counter. When the state machine reaches its last state, it resets the counter and starts over. If a VME access to the board occurs within the first 8 counts after the counter has been reset, then the DAC write pulse is short cycled by the state machine. This causes the DAC output to be updated to an incorrect value, resulting in the possibility of creating a glitch. The glitch may or may not occur depending on the exact timing of the VME access relative to the internal state machine timing.


Reset the state machine counter if a VME bus access occurs within the first 8 counts. The counter is held in reset until the VME access is complete. When the reset is released, the state machine starts again and the DAC write pulse timing is correct, regardless of VME access activity. The implementation of this correction involves changes to the Programmable Array Logic (PAL) device, U40. VMIVME-4512 Boards in the field exhibiting this problem should be returned to GE-Fanuc Embedded Systems for U40 replacement per ECO 00000197.