Deadlock Scenario on VMEbus Single Board Computer


Lock-Up of the Single Board Computer while performing Access to the VMEbus and Sharing Memory to the VMEbus.

A condition exists in systems containing a PCI/VME interface using the Tundra Universe Bridge. The PCI specification allows defines devices called bridges. The specification also allows bridges to buffer data to improve performance. Most of all PCI bridges perform Write-Posting buffers. These allow the Writes from one side of the bridge to be acknowledged before allowing data to be actually written to the other side of the bridge. PCI bridge specification imposes transaction ordering rules on the bridge design to ensure data consistency. One of these rules is that Reads can not transfers the bridge until all Write Posting data has been flushed. This ordering rule and the fact that the VMEbus does not support the ability of a retry creates a potential Deadlock condition. This condition is likely to occur in Systems where there is a high data throughput and a Single board computer is also Sharing some of its Memory to the VMEbus. The Deadlock occurs when the Single Board Computer starts a series of Write to the VMEbus. At the same time, another VMEbus board attempts to Read from the Single board computer's shared Memory. The Deadlock condition will occur if the PCI/VME interface has been granted the PCI bus to perform a Read from the Shared Memory while a write-posted data is destined for the VMEbus is pending in the host bridge. The VMEbus bridge has been granted the PCI bus to perform the Read from Shared Memory. However, the PCI host bridge can not flush (finish) the access to the VMEbus since it can not gain control of the PCI bus. The PCI/VME interface can not complete its Read because the host bridge will not allow the Read to occur. The result is a deadlock condition.


One solution is to never simultaneously enable the VMEbus Master and Slave interface on a VME Single Board Computer. If Shared Memory is needed in a System, there are several commercially available VMEbus Memory boards available. This approach allows the VMEbus arbitration to control all access to the Memory. This will remove the conditions that lead to a deadlock.

If simultaneous VMEbus master/slave operation is required, then the user can use the VMEbus Ownership bit in the MAST_CTL register to guarantee exclusive access to the VMEbus. Correct usage of the bit for this purpose is defined in the Tundra Universe II Based VMEbus Interface manual. For further information, reference Chapter 5 on the PCI/VMEbus Deadlock in the Tundra Universe manual.