Packet Processors Offer Performance and Flexibility for Low-Latency HFT Applications

High frequency trading (HFT) in the financial arena is placing continued demand for the reduction of latencies in the monitoring of stock trades, application of trend analysis algorithms and execution of trading orders. The traditional use of network interface cards uses field programmable gate arrays (FPGAs) to offload the host processor. This approach achieves the goal of reducing latency, but presents challenges to the incorporation of frequent industry and regulatory updates. An alternative approach is to use off-the-shelf PCI Express multi-core packet processor cards and dedicated software to build multi-port HFT compute engines, which results in lowered latency, quicker time-to-market and incorporation of industry and regulatory updates, and lower total cost of ownership of the system.

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