Maximizing Memory Resources on Xeon 5500-based ATCA blades

This paper provides a review of the Intel® 55xx series Nehalem Xeon® processor basic memory subsystem architecture, a discussion of design and application tradeoffs that need to be managed when defining the memory subsystem, and an overview of the main memory resources provided on the GE A10200 AdvancedTCA® Nehalem-based single board computer (SBC). It is assumed that the reader is generally familiar with cache and MMU operation, as well as the NUMA (non-uniform memory architecture) used by Intel and others to optimize physical memory resource allocation for simultaneous data accesses on multiple memory channels.

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